1. Field of the Invention
The invention relates generally to a method of forming an interlayer dielectric film in a semiconductor device, and more particularly to, a method of forming an interlayer dielectric film in a semiconductor device capable of easily burying an insulating material even between metal lines having a narrow gap without voids, in a process of burying the insulating material between the metal lines in order to electrically insulate them.
2. Description of the Prior Art
As a next-generation DRAM is developed, the length of a MOSFET channel used is significantly reduced and the minimum pitch size of word lines and bit lines is also gradually reduced. In a multi-layer metal structure system such as DRAM, further, a method by an insulating spacer is formed on the sidewall of a metal line using nitride or oxide in order to insulate the metal line and a metal plug, has been widely used, which further reduces the distance between the metal lines. In this case, upon deposition of IMD (inter metal dielectric), a gap filling comes to the front as a serious problem.
FIG. 1 shows a layout of a general 8F2 DRAM after the word lines and the bit lines are formed, FIGS. 2A˜2C are cross-sectional views of the device taken along lines A–A′, B–B′ and C–C′ in FIG. 1, and FIGS. 3A˜3C are cross-sectional views of the device taken along lines A–A′, B–B′ and C–C′ in FIG. 1.
Referring now to FIG. 1, FIGS. 2A˜2C and FIGS. 3A˜3C, a word line 13, a word line spacer 14, a first interlayer dielectric film 15, a bit line plug 16, bit lines 17, bit line spacers 18, second interlayer dielectric films 19 and a contact plug 20 are sequentially formed on a semiconductor substrate 11 in which a device isolation film 12 is formed, through a common process.
As mentioned above, in a multi-layer metal structure system such as DRAM, a method of a formation of an insulating spacer (word line spacer or bit line spacer) on the sidewall of a metal line using nitride or oxide has been widely used in order to insulate the metal lines (bit lines or word lines) and a metal plug (bit line plug or contact plug), which thus requires a higher intergeration of the device and further reduces the distance between the metal lines.
FIGS. 4A and 4B are cross-sectional views of the device for explaining a gap filling problem depending on an increased aspect ratio;
Referring to FIG. 1 and FIG. 4A, in order to manufacture a DRAM, a word line 13, a word line spacer 14, a first interlayer dielectric film 15, a bit line plug 16, bit lines 17 and bit line spacers 18 are formed on a semiconductor substrate 11 in which a device isolation film 12 is formed, through a common process.
At this time, the distance “W” between the bit lines 17 is reduced by the width “L” of the bit line spacer, so that an actual distance “W′” between the bit lines is “W-2L”.
Referring to FIGS. 1 and 4B, with the bit lines 17 and the bit line spacer 18 formed, a second interlayer dielectric film 19 is formed on the entire surface for an electrical insulation with upper elements.
At this time, as the aspect ratio between the bit lines 17 is increased by the bit line spacer 18 and the speed where the second interlayer dielectric films 19 are formed below between the bit lines 17 is therefore further faster than that where the second interlayer dielectric films 19 are formed over the bit lines 17, voids A are generated below between the bit lines 17. This degrades an electrical characteristic of the device and reliability of the process.